View ADG1221BRMZ-REEL7_8850706.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low capacitance, low charge injection, 15 v/+12 v i cmos ? dual spst switches adg1221/adg1222/adg1223 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2009 analog devices, inc. all rights reserved. features <0.5 pc charge injection over full signal range off capacitance: 2 pf off leakage: 20 pa supply range: 33 v on resistance: 120 fully specified at 15 v, +12 v no v l supply required 3 v logic-compatible inputs rail-to-rail operation 10-lead msop package applications automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems audio signal routing video signal routing communication systems functional block diagram adg1221 s1 d1 in2 in1 d2 s2 adg1223 s1 d1 in2 in1 d2 s2 adg1222 s1 d1 in2 in1 d2 s2 switches shown for a logic 0 input 06574-001 figure 1. general description the adg1221/adg1222/adg1223 are monolithic, complemen- tary metal-oxide semiconductor (cmos) devices containing four independently selectable switches designed on an i cmos (industrial cmos) process. i cmos is a modular manufacturing process combining high voltage cmos and bipolar technologies. it enables the development of a wide range of high performance analog ics, capable of 33 v operation, in a footprint that no previous generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. the ultralow capacitance and exceptionally low charge injection of these switches make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. figure 2 shows that there is minimum charge injection over the full signal range of the device. the adg1221/adg1222/adg1223 contain two independent single-pole/single-throw (spst) switches. the adg1221 and adg1222 differ only in that the digital control logic is inverted. the adg1221 switches are turned on with logic 1 on the appro- priate control input, and logic 0 is required for the adg1222. the adg1223 has one switch with digital control logic similar to that of the adg1221; the logic is inverted on the other switch. the adg1223 exhibits break-before-make switching action for use in multiplexer applications. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. 0.5 ?0.5 ?15 15 06574-041 input voltage (v) charge injection (pc) 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?10 ?5 0 5 10 t a = 25oc v dd = +15v v ss = ?15v v dd = +5v v ss = ?5v v dd = 12v v ss = 0v figure 2. charge injection vs. input voltage
adg1221/adg1222/adg1223 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply ................................................................................. 4 ? absolute maximum ratings ............................................................ 6 ? thermal resistance .......................................................................6 ? esd caution...................................................................................6 ? pin configuration and function descriptions ..............................7 ? terminology .......................................................................................8 ? typical performance characteristics ..............................................9 ? test circuits ..................................................................................... 13 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 3/09rev. 0 to rev. a changes to power requirements, i dd , digital inputs = 5 v parameter, table 1 ............................................................................. 4 changes to t on parameter and power requirements, i dd , digital inputs = 5 v parameter, table 2 ...................................................... 5 2/07rev. 0: initial version
adg1221/adg1222/adg1223 rev. a | page 3 of 16 specifications dual supply v dd = 15 v 10%, v ss = C15 v 10%, gnd = 0 v, unless otherwise noted. table 1. temperature parameter 25c C40c to +85c C40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on v dd = +13.5 v, v ss = C13.5 v, v s = 10 v, i s = C1 ma (see figure 23) 120 typ 200 240 270 max on resistance match between channels, ?r on v s = 10 v, i s = C1 ma 2.5 typ 6 10 12 max on resistance flatness, r flat(on) v s = C5 v/0 v/+5 v; i s = C1 ma 20 typ 64 76 83 max leakage currents v dd = +16.5 v, v ss = C16.5 v source off leakage, i s (off) v s = 10 v, v d = 10 v (see figure 24) 0.002 na typ 0.1 0.6 1 na max drain off leakage, i d (off) v s = 10 v, v d = 10 v (see figure 24) 0.002 na typ 0.1 0.6 1 na max channel on leakage, i d , i s (on) v s = v d = 10 v (see figure 25) 0.01 na typ 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh v in = v inl or v inh 0.005 a typ 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 1 t on r l = 300 , c l = 35 pf, v s = 10 v (see figure 26) 130 ns typ 170 210 240 ns max t off r l = 300 , c l = 35 pf, v s = 10 v (see figure 26) 85 ns typ 105 130 140 ns max break-before-make time delay (adg1223 only), t bbm r l = 300 , c l = 35 pf, v s1 = v s2 = 10 v (see figure 27) 40 ns typ 10 ns min charge injection, q inj 0.1 pc typ v s = 0 v, r s = 0 , c l = 1 nf (see figure 28) off isolation 75 db typ r l = 50 , c l = 1 pf, f = 1 mhz (see figure 29)
adg1221/adg1222/adg1223 rev. a | page 4 of 16 temperature parameter 25c C40c to +85c C40c to +125c unit test conditions/comments channel-to-channel crosstalk 90 db typ r l = 50 , c l = 1 pf, f = 1 mhz (see figure 30) total harmonic distortion + noise, thd + n 0.15 % typ r l = 10 k, 5 v rms, f = 20 hz to 20 khz C3 db bandwidth 960 mhz typ r l = 50 , c l = 1 pf (see figure 31) c s (off) v s = 0 v, f = 1 mhz 1.7 pf typ 2.2 pf max c d (off) v s = 0 v, f = 1 mhz 1.7 pf typ 2.2 pf max c d , c s (on) v s = 0 v, f = 1 mhz 3 pf typ 4 pf max power requirements v dd = +16.5 v, v ss = C16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max digital inputs = 0 v or v dd 140 a typ digital inputs = 5 v 190 a max digital inputs = 5 v i ss digital inputs = 0 v, 5 v, or v dd 0.001 a typ 1.0 a max v dd /v ss 5/16.5 v min/max gnd = 0 v 1 guaranteed by design, not subject to production test. single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. temperature parameter 25c C40c to +85c C40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on v dd = 10.8 v, v ss = 0 v, v s = 0 v to 10 v, i s = C1 ma (see figure 23) 300 typ 475 567 625 max on resistance match between channels, ?r on v s = 0 v to 10 v, i s = C1 ma 4.5 typ 16 26 27 max on resistance flatness, r flat(on) 60 typ v s = 3 v/6 v/9 v, i s = C1 ma leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) v s = 1 v/10 v, v d = 10 v/1 v (see figure 24) 0.002 na typ 0.1 0.6 1 na max drain off leakage, i d (off) v s = 1 v/10 v, v d = 10 v/1 v (see figure 24) 0.002 na typ 0.1 0.6 1 na max
adg1221/adg1222/adg1223 rev. a | page 5 of 16 temperature parameter 25c C40c to +85c C40c to +125c unit test conditions/comments channel on leakage, i d , i s (on) v s = v d = 1 v or 10 v (see figure 25) 0.01 na typ 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh v in = v inl or v inh 0.001 a typ 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 t on r l = 300 , c l = 35 pf, v s = 8 v (see figure 26) 190 ns typ 250 300 345 ns max t off r l = 300 , c l = 35 pf, v s = 8 v (see figure 26) 120 ns typ 150 190 225 ns max break-before-make time delay (adg1223 only), t bbm r l = 300 , c l = 35 pf, v s1 = v s2 = 8 v (see figure 27) 70 ns typ 10 ns min charge injection, q inj 0.2 pc typ v s = 6 v, r s = 0 , c l = 1 nf (see figure 28) off isolation 75 db typ r l = 50 , c l =1 pf, f = 1 mhz (see figure 29) channel-to-channel crosstalk 90 db typ r l = 50 , c l = 1 pf, f = 1 mhz (see figure 30) ?3 db bandwidth 550 mhz typ r l = 50 , c l = 1 pf (see figure 31) c s (off) v s = 6 v, f = 1 mhz 2.1 pf typ 2.6 pf max c d (off) v s = 6 v, f = 1 mhz 2.1 pf typ 2.6 pf max c d , c s (on) v s = 6 v, f = 1 mhz 3.8 pf typ 4.6 pf max power requirements v dd = 13.2 v i dd 0.001 a typ digital inputs = 0 v or v dd 1.0 a max digital inputs = 0 v or v dd 140 a typ digital inputs = 5 v 190 a max digital inputs = 5 v v dd 5/16.5 v min/max v ss = 0 v, gnd = 0 v 1 guaranteed by design, not subject to production test.
adg1221/adg1222/adg1223 rev. a | page 6 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd C0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog inputs 1 v ss C 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 gnd C 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current per channel, s or d 30 ma operating temperature range C40c to +125c storage temperature range C65c to +150c junction temperature 150c reflow soldering peak temperature, pb free 260c 1 overvoltages at in, s, or d are clamped by internal diodes. current must be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jc unit 10-lead msop (4-layer board) 206 44 c/w esd caution
adg1221/adg1222/adg1223 rev. a | page 7 of 16 pin configuration and fu nction descriptions 06574-002 in1 1 s1 2 d1 3 in2 10 v dd 9 gnd 8 d2 4 nc 7 s2 5 v ss 6 nc = no connect adg1221/ adg1222/ adg1223 top view (not to scale) figure 3. 10-lead ms op pin configuration table 5. pin function descriptions pin no. mnemonic description 1 in1 logic control input. 2 s1 source terminal. can be an input or output. 3 d1 drain terminal. can be an input or output. 4 d2 drain terminal. can be an input or output. 5 s2 source terminal. can be an input or output. 6 v ss most negative power supply potential. 7 nc no connect. 8 gnd ground (0 v) reference. 9 v dd most positive power supply potential. 10 in2 logic control input. table 6. adg1221/adg1222 truth table adg1221 inx adg1222 inx switch condition 1 0 on 0 1 off table 7. adg1223 truth table adg1223 inx switch 1 condition switch 2 condition 0 off on 1 on off
adg1221/adg1222/adg1223 rev. a | page 8 of 16 terminology i dd the positive supply current. i ss the negative supply current. v d (v s ) the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl (i inh ) the input current of the digital input. c s (off) the off switch source capacitance, measured with reference to ground. c d (off) the off switch drain capacitance, measured with reference to ground. c d , c s (on) the on switch capacitance, measured with reference to ground. c in the digital input capacitance. t on the delay between applying the digital control input and the output switching on (see figure 26). t off the delay between applying the digital control input and the output switching off (see figure 26). t bbm off time or on time measured between the 90% points of both switches, when switching from one address state to another (adg1223 only). q inj (charge injection) a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. C3 db bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. thd + n (total harmonic noise plus distortion) the ratio of the harmonic amplitude plus noise of the signal to the fundamental. acpsrr (ac power supply rejection ratio) measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p. the ratio of the amplitude of signal on the output to the amplitude of the modulation is the acpsrr.
adg1221/adg1222/adg1223 rev. a | page 9 of 16 typical performance characteristics v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v source or drain voltage (v) on resistance ( ? ) 200 180 160 140 120 100 60 80 0 20 40 ?18 ?15 ?12 ?9 ?6 ?3 3 9 15 061218 06574-003 v dd = +13.5v v ss = ?13.5v t a = 25c figure 4. on resistance as a function of v s (v d ), dual supply source or drain voltage (v) on resistance ( ? ) 450 400 350 300 250 150 200 0 50 100 ?5 ?4 ?3 ?2 ?1 2 4 01 3 5 06574-004 v dd = +5.5v v ss = ?5.5v t a = 25c figure 5. on resistance as a function of v s (v d ), dual supply v dd = 13.2v v ss = 0v source or drain voltage (v) on resistance ( ? ) 450 400 350 300 250 150 200 0 50 100 024681012 06574-005 v dd = 12v v ss = 0v v dd = 10.8v v ss = 0v t a = 25c figure 6. on resistance as a function of v s (v d ), single supply source or drain voltage (v) on resistance ( ? ) 250 150 200 0 50 100 ?15 ?10 ?5 0 5 10 15 06574-006 v dd = +15v v ss = ?15v t a = +125c t a = +25c t a = +85c t a = ?40c figure 7. on resistance as a function of v s (v d ) for different temperatures, dual supply source or drain voltage (v) on resistance ( ? ) 600 400 500 300 200 0 100 024681012 06574-007 v dd = 12v v ss = 0v t a = +125c t a = +25c t a = +85c t a = ?40c figure 8. on resistance as a function of v s (v d ) for different temperatures, single supply leakage current (pa) 0 ?450 ?400 08 0 06574-018 200 150 100 50 ?50 ?100 ?150 ?200 ?250 ?300 ?350 20 40 60 100 120 v dd = +15v v ss = ?15v v bias = 10v temperature (oc) i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) + + i d , i s (on) ? ? figure 9. leakage current as a function of temperature, dual supply
adg1221/adg1222/adg1223 rev. a | page 10 of 16 leakage current (pa) 0 ?250 100 08 0 06574-020 150 ?50 ?100 ?150 ?200 50 20 40 60 100 120 temperature (oc) i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) + + i d , i s (on) ? ? v dd = +5v v ss = ?5v v bias = 4.5v figure 10. leakage current as a function of temperature, dual supply leakage current (pa) 0 ?200 100 08 0 06574-019 300 250 200 150 ?50 ?100 ?150 50 20 40 60 100 120 temperature (oc) i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) + + i d , i s (on) ? ? v dd = 12v v ss = 0v v bias = 1/10v figure 11. leakage current as a function of temperature, single supply 120 0 0 06574-049 logic level, inx (v) i dd (a) v dd = 12v v ss = 0v v dd = +15v v ss = ?15v i dd per channel t a = 25oc 100 80 60 40 20 2 4 6 8 101214 figure 12. i dd vs. logic level 0.5 ?0.5 ?15 15 06574-041 input voltage (v) charge injection (pc) 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?10 ?5 0 5 10 t a = 25oc v dd = +15v v ss = ?15v v dd = +5v v ss = ?5v v dd = 12v v ss = 0v figure 13. charge injection vs. input voltage 300 0 ?40 120 06574-045 temperature (oc) time (ns) 250 200 150 100 50 ?200 20406080100 15v ds t on 15v ds t off 12v ss t on 12v ss t off figure 14. t on /t off vs. temperature iso l a tion (db) ?100 10k 06574-025 0 1g frequency (hz) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 100k 1m 10m 100m v dd = +15v v ss = ?15v t a = 25oc figure 15. off isol ation vs. frequency
adg1221/adg1222/adg1223 rev. a | page 11 of 16 crosstalk (db) ?120 10k 06574-021 0 1g frequency (hz) ?20 ?40 ?60 ?80 ?100 100k 1m 10m 100m v dd = +15v v ss = ?15v t a = 25oc figure 16. crosstalk vs. frequency insertion loss (db) ?24 ?12 10k 06574-029 0 1g frequency (hz) ?16 ?18 ?20 ?22 ?14 ?2 ?4 ?6 ?8 ?10 100k 1m 10m 100m 100m v dd = +15v v ss = ?15v t a = 25oc figure 17. insertion loss vs. frequency 0 ?100 100k 1m 10m 06574-052 frequency (hz) psrr (db) 100m ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 v dd = +15v v ss = ?15v vp-p = 0.63v t a = 25oc decoupling caps on no decoupling caps on figure 18. acpsrr vs. frequency frequency (hz) thd + n (%) 10 1 0.1 0.01 10 100 1k 10k 100k load = 10k ? t a = 25c v dd = +5v, v ss = ?5v, v s = +3.5v rms v dd = +15v, v ss = ?15v, v s = +5v rms 0 6574-053 figure 19. thd + n vs. frequency
adg1221/adg1222/adg1223 rev. a | page 12 of 16 5.0 0 ?15 15 06574-035 bias voltage (v) capacitance (pf) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ?10 ?5 0 5 10 v dd = +15v v ss = ?15v t a = 25oc source/drain on source off drain off figure 20. capacitance vs. bias voltage 5.0 0 012 06574-036 bias voltage (v) capacitance (pf) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 246810 v dd = 12v v ss = 0v t a = 25oc source/drain on source off drain off figure 21. capacitance vs. bias voltage 5.0 0 ?5 5 06574-037 bias voltage (v) capacitance (pf) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ?4 ?3 ?2 ?1 0 1 2 3 4 source/drain on source off drain off v dd = +5v v ss = ?5v t a = 25oc figure 22. capacitance vs. bias voltage
adg1221/adg1222/adg1223 rev. a | page 13 of 16 test circuits i ds v1 sx dx v s r on = v1/i ds 06574-008 figure 23. test circuit 1on resistance sx dx v s a a v d i s (off) i d (off) 06574-009 figure 24. test circuit 2off leakage sx dx a v d i d (on) nc nc = no connect 06574-010 figure 25. test circuit 3on leakage v s inx sx dx gnd r l 300 ? c l 35pf v out v dd v ss 0.1f v dd 0.1f v ss adg1222 adg1221/ adg1222 adg1221 v in v in v out t on t off 50% 50% 90% 90% 50% 50% 06574-011 figure 26. test circuit 4switching times v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300? c l 35pf v out2 v out1 v dd v ss 0.1f v dd 0.1f v ss v in v out1 v out2 adg1223 t d t d 50% 50% 90% 90% 90% 90% 0v 0v 0v r l 300 ? c l 35pf 06574-012 figure 27. test circuit 5break-before-make time delay inx v out adg1222 adg1221/ adg1222 adg1221 v in v in v out off v out on q inj = c l v out sx dx v dd v ss v dd v ss v s r s gnd c l 1nf 06574-013 figure 28. test circuit 6charge injection
adg1221/adg1222/adg1223 rev. a | page 14 of 16 v out network analyzer r l 50? 50? inx v in sx dx 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 06574-014 adg1221/adg1222/ adg1223 figure 29. test circuit 7off isolation channel-to-channel crosstalk = 20 log v out gnd adg1221/adg1222/ adg1223 s1 dx s2 v out network analyzer r l 50? 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 06574-015 figure 30. test circuit 8ch annel-to-channel crosstalk v out network analyzer r l 50? v in insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 06574-016 50? inx sx dx adg1221/adg1222/ adg1223 figure 31. test circuit 9bandwidth v out audio precision r l 10k ? v in v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 06574-017 r s 50 ? inx sx dx adg1221/adg1222/ adg1223 figure 32. test circuit 10total harmonic distortion + noise
adg1221/adg1222/adg1223 rev. a | page 15 of 16 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 33. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model temperature range package desc ription package option branding adg1221brmz 1 ?40c to +125c 10-lead mini small outline package (msop) rm-10 s27 ADG1221BRMZ-REEL7 1 ?40c to +125c 10-lead mini small outline package (msop) rm-10 s27 adg1222brmz 1 ?40c to +125c 10-lead mini small outline package (msop) rm-10 s28 adg1222brmz-reel7 1 ?40c to +125c 10-lead mini small outline package (msop) rm-10 s28 adg1223brmz 1 ?40c to +125c 10-lead mini small outline package (msop) rm-10 s2j adg1223brmz-reel7 1 ?40c to +125c 10-lead mini small outline package (msop) rm-10 s2j 1 z = pb-free part.
adg1221/adg1222/adg1223 rev. a | page 16 of 16 notes ?2007C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06574-0-3/09(a)

▲Up To Search▲

Price & Availability of ADG1221BRMZ-REEL7

	To Download ADG1221BRMZ-REEL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .